P241 — AIEP — Deterministic Simulation Coprocessor

Applicant: Neil Grassby Classification: Patent Application — Confidential Priority: Claims priority from GB2519711.2 filed 20 November 2025 Architecture Layer: AIEP Phase 2 Hardware Layer

Framework Context

[0001] This specification operates within an AIEP environment as defined in GB2519711.2 and GB2519798.9. The present specification defines a dedicated hardware coprocessor that accelerates deterministic simulation of counterfactual world-state branches for the AIEP Hypothesis Simulation Engine (P204) and Counterfactual Timeline Engine (P203).

Field of the Invention

[0002] The present invention relates to dedicated hardware coprocessor architectures for deterministic counterfactual simulation in evidence-bound AI systems.

Background

[0003] Counterfactual simulation in AIEP requires maintaining multiple parallel world-state branches, each derived from the current CWSG with specific hypothetical interventions applied. Software-only simulation is computationally expensive when exploring large branch trees. A dedicated coprocessor purpose-built for deterministic graph state manipulation enables simulation throughput several orders of magnitude beyond general-purpose compute for this workload class.

Summary of the Invention

[0004] The invention provides a Deterministic Simulation Coprocessor (DSC) comprising: a high-bandwidth causal graph memory subsystem storing multiple version snapshots of the CWSG; a parallel branch execution array capable of evaluating N independent causal simulation threads simultaneously; a deterministic execution unit ensuring identical outputs for identical inputs across all simulation threads; a branch isolation mechanism preventing state contamination between concurrent counterfactual threads; and a hardware evidence hash accelerator producing branch certification hashes natively during simulation.

ASCII Architecture

Host AIEP System → Simulation Dispatch Interface
                            |
                            v
+-----------------------------------------------+
| Deterministic Simulation Coprocessor (DSC)    |
|                                               |
|  CWSG Version Snapshot Memory                |
|  Parallel Branch Execution Array (N threads) |
|  Deterministic Execution Unit                |
|  Branch Isolation Controller                 |
|  Evidence Hash Accelerator                   |
+---------------------+-------------------------+
                      |
              Branch Results + Certification Hashes
                      |
                      v
              Host Simulation Engine (P203/P204)

Detailed Description

[0005] CWSG Version Snapshot Memory. The coprocessor maintains a high-bandwidth scratchpad memory capable of storing the CWSG in multiple independent version snapshots. Each counterfactual branch operates on its own snapshot, preventing branch contamination. The host system writes the root CWSG state to the coprocessor before simulation dispatch.

[0006] Parallel Branch Execution Array. The coprocessor contains N parallel execution units, each capable of applying causal step operations to a branch snapshot. Parallelism enables N branches to be evaluated simultaneously, with branch results collected and returned to the host system in a single batch.

[0007] Determinism Guarantee. The execution units enforce strict determinism: floating-point operations are performed in fixed-width bounded arithmetic; randomisation is suppressed; execution order is fixed. This ensures that supplying identical inputs produces bit-identical outputs on every execution.

[0008] Evidence Hash Accelerator. A dedicated hash unit produces a content-addressable hash of each branch state at each simulation step natively in hardware, without requiring the host CPU to perform hashing. These hashes form the branch certification chain used by P233.

Technical Effect

[0009] The invention provides hardware-accelerated, deterministic counterfactual branch simulation for evidence-bound AI systems. By executing N branches in parallel on isolated memory snapshots, the coprocessor delivers N-fold simulation throughput compared to sequential host-CPU execution. By enforcing fixed-width bounded arithmetic, suppressed randomisation, and fixed execution order in dedicated hardware execution units, the coprocessor guarantees bit-identical outputs from identical inputs—enabling reliable cross-node replay verification. The native evidence hash accelerator produces branch certification hash chains at hardware speed, eliminating the CPU load of sequential SHA-256 computation on the critical simulation path.

Claims

1. A method of executing deterministic counterfactual simulation in an evidence-bound artificial intelligence system, comprising the steps of: (a) receiving from a host system a root CWSG state and a set of counterfactual branch intervention specifications, and writing the root state to CWSG version snapshot memory; (b) allocating one independent branch snapshot per intervention specification and dispatching each snapshot to a corresponding execution unit in the parallel branch execution array; (c) executing causal step operations on each branch snapshot in each execution unit with determinism enforced by fixed-width bounded arithmetic, suppressed randomisation, and fixed execution order; (d) at each simulation step, generating a content-addressable hash of branch state via the dedicated evidence hash accelerator unit, appending the hash to that branch’s certification hash chain; (e) upon completion, returning all branch results and complete certification hash chains to the host system in a single batch.

2. The method of claim 1, wherein each execution unit operates concurrently on a distinct isolated branch snapshot, preventing state contamination between branches.

3. The method of claim 1, wherein fixed-width bounded arithmetic is applied to all arithmetic operations including floating-point operations, and randomisation sources are suppressed for all execution units.

4. The method of claim 1, wherein the certification hash chains produced in step (d) are formatted for direct consumption by the Evidence-Bound Simulation Certification Engine.

5. The method of claim 1, further comprising evicting a branch snapshot slot on completion of its branch and making the slot available for a new branch assignment without full re-initialisation.

6. A deterministic simulation coprocessor for an evidence-bound artificial intelligence system, comprising: a CWSG version snapshot memory storing multiple independent branch state copies; a parallel branch execution array comprising N execution units each coupled to a dedicated branch snapshot slot; determinism enforcement hardware in each execution unit applying fixed-width bounded arithmetic and suppressed randomisation; and an evidence hash accelerator unit producing content-addressable branch state hashes natively at each simulation step.

7. A computer-readable medium carrying firmware for a simulation coprocessor, the firmware configured to implement the method of any preceding method claim.

Abstract

A deterministic simulation coprocessor for evidence-bound artificial intelligence accelerates counterfactual world-state simulation by maintaining a CWSG version snapshot memory storing multiple independent branch copies and executing N branches in parallel on isolated execution units with hardware-enforced determinism. Fixed-width bounded arithmetic, suppressed randomisation, and fixed execution ordering in all units guarantee bit-identical outputs from identical inputs. A dedicated evidence hash accelerator unit generates branch state certification hash chains at each simulation step natively in hardware, eliminating host-CPU hashing overhead on the critical simulation path and producing hash chains directly consumed by the Evidence-Bound Simulation Certification Engine.